Embedded silicon germanium (e-SiGe) sources and drains have been used successfully in bulk planar p-channel field effect transistors (p-FETs) as an efficient method to induce strain in the p-FET channel. In general a FET includes a source and a drain connected by at least one channel and a gate that regulates current flow through the channel(s). The compressive strain increases the hole mobility and therefore the device drive current.
The process used for e-SiGe sources and drains in bulk planar p-FETs includes etching out the source and drain region of the p-FET in silicon (Si) and then epitaxially growing a source and a drain region from SiGe. Due to the lattice mismatch between SiGe and Si (with SiGe having a large lattice constant), the source and drain regions induce a compressive strain in the p-FET channel.
For further scaling of complementary metal-oxide semiconductor (CMOS) technology, non-planar devices such as FinFETs and nanowire FETs exhibit superior short channel control than is achievable with planar bulk FETs. Unfortunately, it is not possible to use e-SiGe in its present known form to strain the FET channel in these non-planar devices. The main reason the e-SiGe process is not compatible with these non-planar FET geometries is that the channel is made up of a very thin body (such as a fin or a nanowire). Etching out the channel extensions in order to replace them with epitaxial SiGe is not possible since there is no substrate from which epitaxial SiGe can seed.
Therefore, techniques integrating e-SiGe sources and drains with non-planar FET devices, such as FinFETs and nanowire FETs, would be desirable.